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Electronics & Communication

 



Mr. Anuj Kumar Maurya
Assistant Professor (GRADE-I)

Email : anuj.maurya@mail.jaypeeu.ac.in

Tel : +91-7060120858, 8410787450

 

 

 

Education

M.Tech - IIT (BHU) Varanasi (2014)
B.Tech - UPTU, Lucknow (2012)

Other Qualifications: 

GATE 2011, 2012, 2013, 2014.2015


Biography

Mr. Anuj Kumar Maurya received his M.Tech from Indian Institute of Technology (BHU) Varanasi with specialization in Microelectronics in 2014. He completed his B.Tech from Uttar Pradesh Technical University, Lucknow in 2012. He got 98.57, 99.64 and 99.85 percentile in Gate 2011, 2012 and 2013, respectively. He has been awarded with Academic Excellence Award in 2009 and 2010 by Sharda Group of Institution. He is associated with Jaypee University, Anoopshahr as an Assistant Professor from Aug 2014.


Interest Area(s)

VLSI, Microelectronics, CMOS Technology, IC Fabrication, Solid State Devices, Digital Logic Design, Hybrid IC design, Network Theory


Publications
  1. Singh, M.; Maurya, A. K.; Singh, S. P.; Balasubramanian, S. K.; “6×6 booth multiplier implemented in modified split-path data driven dynamic logic” IEEE - Engineering and Systems (SCES), Allahabad, pp. 1-4, 2014
  2. Varun Goel and Anuj Kumar Maurya, “Analytical Model for Surface Potential of Graded-Channel SOI MOSFETs,” International Conference on Advanced and Agile Manufacturing Systems (ICAM-2015), KNIT Sultanpur, India, December 28-29, 2015.
  3. Varun Goel; Anuj Kumar Maurya; Sanjay Sharma; Sanjay Kumar, “Study of role of channel engineering and gate engineering in silicon-on-insulator (SOI) MOSFETs using 2-D analytical modeling”, 3rd International Conference on Emerging Electronics, IEEE, pp. 1-5, 2016.

  4. Varun Goel; Abhay Kumar; Sidhartha Sankar Rout; Anuj Kr Maurya; Sanjay Sharma; Sanjay Kumar, “2-D analytical model of surface potential for graded-channel-double-gate (GCDG) MOSFETs”, International Conference on Signal Processing and Communication, IEEE, pp. 448-451, 2016.



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